UVM-MS Working Group
The UVM-MS Working Group will focus on the standardization of analog/mixed-signal extensions (AMS) for the Universal Verification Methodology (UVM) standard. A UVM-MS standard will provide a unified approach which allows UVM to be more mixed-signal aware, resulting in the improved verification of analog/mixed-signal components and sub-systems.
Chair: Tom Fitzpatrick, Siemens EDA
Vice-Chair: Tim Pylant, Cadence
The objective of the UVM-MS Working Group is to standardize a method for driving and monitoring mixed-signal nets within UVM including stimulus, score-boarding and analysis. The working group will also define a framework for creation of mixed-signal verification components by extending existing digital-centric verification IP. For more information read the press release.
There have been many discussions in recent years about the need to make UVM more mixed-signal aware. Various proposals have been presented at recent DVCon events addressing the need for AMS extensions for UVM to enrich and improve the verification of analog/mixed-signal products and applications. Most of these proposals offer similar capabilities but often use a different implementation to resolve existing constraints enforced by UVM or by limitations caused by mixing languages such as SystemVerilog and Verilog-AMS.
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If you are an employee of an Accellera member company and wish to participate in this working group, please log in or create an account in the Accellera Workspace. Once you are logged in to the Workspace, select "View Workgroups", select UVM-AMS Working Group, and click the Join button.