Join Accellera at DVCon U.S. 2024

DVCon U.S. 2024We hope to see you during DVCon U.S. March 4-7 in San Jose, California. Accellera working groups have a lot to share during the conference and exhibition. For more information on the conference program and to register, visit the DVCon U.S. website.

The following DVCon events are open to registered DVCon attendees (these events are not part of the free registration option).


Accellera Luncheon

Focused on Federated Simulation, featuring speakers from Ford Motor Company and the Federated Simulation Standard Proposed Working Group

DVCon U.S. 2024 Preview from Martin Barnasconi

Martin Barnasconi, Accellera Technical Committee Chair, gives a brief description of the Accellera activities attendees can look forward to.

Monday, March 4

Join Accellera for an informative luncheon focused on the efforts and direction of the Federated Simulation Standard Proposed Working Group (FSS PWG). The luncheon will begin with an update on Accellera working group activity from Chair Lu Dai, followed by the presentation of a Distinguished Service Award to a long-time friend of Accellera.

Mark Burton, the FSS PWG Vice Chair will then discuss the intent of the PWG and what attendees can look forward to from the potential standard.  He will be joined by Yury Bayda, Principal Software Engineer at Ford Motor Company, who will discuss how such a standard will be beneficial to Ford. We hope you’ll join us!


Portable Stimulus Tutorial

Efficient Portable Programming Sequence Development with PSS

Monday, March 4

In addition to discussing portable programming sequence development with Portable Stimulus (PSS), this tutorial will also provide an overview of the PSS features in development for PSS 3.0, as well as an introduction to the PSS methodology library currently under development by the working group.


IP-XACT Workshop

An Introduction to IP-XACT

Monday, March 4

This workshop will explain basic usage of IP-XACT IEEE 1685-2022 for IP re-use and integration flows as well as the data model underlying the standard. During the workshop, presenters will address IP-XACT concepts that are relevant to understand the overall SoC data model such as components; design and design configurations; bus and abstraction definition; component memory maps and registers; component address spaces and bus interface bridges; and type definitions.


CDC Workshop

Hierarchical CDC and RDC Closure with Standard Abstract Models

Monday, March 4

As complexity and the number of clock domains increase in today’s ASIC designs, we are moving towards a hierarchical verification approach. This workshop will cover the proven Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) schemes, the verification challenges, and the potential risk mitigation strategies. Presenters will then discuss the hierarchical CDC/RDC verification methodology, the tradeoffs, and the challenges. The workshop will highlight the CDC standard and summarize the status of the current efforts.


Functional Safety Workshop

White Paper Review and What’s Next

Monday, March 4

The implementation of Functional Safety standards such as ISO26262 poses challenges during the exchange and integration of functional safety data between different work products and activities that are carried out by different teams and/or different layers of the supply chain. Automation with EDA tools is now common practice in this field, but interoperability is still challenged by the lack of a Functional Safety standard that supports the data exchange. This workshop will review the working group’s recent white paper that describe the approach taken to develop the data model and a corresponding language prototype that will enable Functional Safety data exchange.


UVM Workshop

An Update on New Features and Open Q&A

Monday, March 4

The Accellera UVM Working Group released the IEEE 1800.2-2020-2.0 reference library last year. Since that release, the group has been working on a public GitHub repository to give users enhanced access to the latest bug fixes and to provide bug fix suggestions. During the workshop, presenters will provide the details of the new features and explain the plan to interact with users via the public repository.


IEEE P3164 Workshop

A Practical Guide to SA-EDI Methodology

Monday, March 4

This workshop will demonstrate how to identify assets in intellectual property (IP) in accordance with Accellera’s Security Annotation for Electronic Design Integration (SA-EDI) standard. This guidance is planned to be documented in the IEEE P3164 Asset Identification white paper.

The white paper introduces a methodical and practical approach that can be applied by IP owners with limited experience in security practices. The methodology is vetted using four example IPs, ranging from simple to complex, to highlight how an IP developer can use them to produce accurate SA-EDI collateral for the IC owner to properly consume and apply. Don't miss this opportunity to enhance your knowledge in security.

Thank you to our 2024 Global Sponsors

CadenceSiemens EDASynopsys