Community Newsletter: February 2021
IN THIS ISSUE:
- Message from the Chair
- 2021 is off and running and there’s much to look forward to
- Working Group News
- UVM Reference Implementation Aligned with IEEE 1800.2-2020
- Upcoming Events
- Accellera Day at DVCon U.S. 2021 includes a tutorial on Portable Stimulus, five short workshops and a UVM Birds of a Feather sponsored by Accellera
- The SystemC Evolution Continues with Quarterly Fika Events
- DVCon China 2021
- Stay tuned for updates on other Accellera-sponsored events in 2021
- IEEE Get Program Update
Welcome to 2021! I hope everyone had a safe and happy holiday and that the new year is off to a good start for each of you.
We are off and running at Accellera. We recently elected our new Board of Directors and Officers for this year. We have added Sandeep Mehndiratta, Synopsys and Aparna Dey, Cadence to our Board. Aparna joins us as our longtime Board member, Stan Krolikoski, is transitioning toward retirement. Stan has been with Accellera since its inception, working tirelessly to advance and promote our standards efforts. Aparna also joins our Officers as Treasurer, and Board member Martin Barnasconi, NXP Semiconductors joins our Officers as Secretary. All other Board members and Officers remain the same.
I would like to extend a warm welcome the newest members of our Accellera family: AEDVICES, Agnisys, Arteris IP, Huawei and Microchip have joined as Associate Members and Batelle, Carinthia University, and TU Dortmund have joined as our newest University Members.
Our working groups continue to make great progress. The Functional Safety Working Group is publishing their whitepaper in the coming weeks, while the SystemC AMS Working Group is releasing their regression suite this quarter. The UVM-AMS Working Group is also scheduled to deliver a whitepaper soon, and the SystemC Verification Working Group is focused on delivering their UVM-SystemC Reference Implementation. In just a few weeks the much-anticipated emerging IP Security Assurance standard will have a public review, and the Portable Test and Stimulus Standard 2.0 will be released to an eager community.
Although COVID-19 forced most of our conferences to pivot to virtual gatherings, including our upcoming DVCon U.S., DVCon China will venture into a face-to-face event for the local community in what we hope is a broadening of the post-pandemic era. Our other conferences continue to assess the local guidelines and situations carefully and will adapt events accordingly.
Our experience with virtual events during quarantine has created some new opportunities as well. Our annual SystemC Evolution Day event has seen such tremendous interest and growth in participation that it is planning quarterly events beginning this March.
Accellera enjoys a close working relationship with the IEEE, and we continue to have multiple ongoing collaborations on standards. In the coming year we plan to hand over an update of IP-XACT, continue the development of a SystemC Synthesis LRM and SystemVerilog AMS LRM, as well as collaborate to update the Reference Implementation for IEEE P1666 SystemC.
I would also like to remind you that we encourage all of our members to participate in working group developments, continue to provide feedback on whitepapers and public reviews, join the conversations in our forums, and join our conferences and webinars throughout the year and around the globe. Stay involved, make your voice heard, and help shape standards the way you would like to see them evolve.
We are looking forward to a successful 2021 with an end to the virus in sight.
Lu Dai, Accellera Systems Initiative Chair
The UVM Working Group has completed work on its UVM-2020 1.0 reference implementation, aligning it with the latest IEEE 1800.2-2020 Standard for UVM.
The new library implementation provides the latest UVM standard API along with some additional debug API that provides a more cohesive package with the 1800.2-2020 API. The errata fixes better align the implementation behavior with the LRM documentation. More detail on the additions and fixes can be found in the documentation provided with the release.
The UVM-2020 1.0 reference implementation can be downloaded for free from Accellera. The IEEE 1800.2-2020 standard is available free of charge from the IEEE Get program, courtesy of Accellera. Visit the UVM forum to provide feedback, ask questions, and engage in discussions. For more information on UVM, visit the UVM community page.
DVCon U.S. will be held March 1-4 on a virtual platform and will offer attendees a combination of recorded presentations and live Q&A to provide an interactive, high-quality virtual experience.
Keeping with tradition, Accellera Day opens the conference on March 1 with a tutorial, five short workshops and a UVM Birds of a Feather presented by Accellera working groups.
Accellera-sponsored tutorial on Monday, March 1:
“Portable Stimulus 2.0 is Here: What You Need to Know” will be presented from 9:00am-11:00am by members of the Portable Stimulus Working Group. Members will share some of the important new features coming in v2.0 of the Portable Test and Stimulus Standard that were added to enhance the usability, programmability, and portability of the standard.
Accellera-sponsored short workshops on Monday, March 1 include:
- “UVM-SystemC Randomization-Updates from the SystemC Verification Working Group” presented from 9:00am-10:00am by members of the SystemC Verification Working Group. The workshop will introduce the basic concepts of UVM-SystemC and show how constrained randomization and functional coverage can be integrated to build a verification environment using the current UVM-SystemC library. Currently, the working group is working on the standardization of a common randomization layer based on CRAVE, a C++ and SystemC constraint randomization library. The workshop will show how constrained randomization can be used within SystemC and integrated into UVM-SystemC verification environments.
- “Getting to Know Accellera’s Emerging Hardware Security Standard: Security Annotation for Electronic Design Integration” presented by members of the IP Security Assurance Working Group from 9:00am-10:00am. This workshop will introduce an emerging new standard called Security Annotation for Electronic Design Integration (SA-EDI) to address security concerns in a manner that is low-overhead, non-disruptive, and scalable across IP families. The standard specifies an approach to provide information about the IP security relevant to the integrator and recommended mitigations to implement and risk to address. At the conclusion of this session, attendees will better understand risks associated with IP and become familiar with the SA-EDI standard, including how it can be applied and when it will be available for reference.
- “UVM-AMS: A UVM-Based Analog Verification Standard” will be presented by members of the UVM-AMS Working Group from 11:30am-12:30pm. Members will share the work done so far in developing a comprehensive and unified analog/mixed-signal verification methodology based on UVM to improve analog mixed signal and digital mixed signal verification of integrated circuits and systems.
- “Multi-Language Verification Framework Standardization and Demo” will be presented by members of the Multi-Language Verification Working Group (MLVWG) from 11:30am-12:30pm. In this workshop, the MLVWG presents the current status of the proof-of-concept implementation and demonstrates its capabilities. A multi-language example is presented, which combines the UVM library in SystemVerilog and SystemC. Based on this example, the multi-language verification framework, its foundation concepts and the API targeted for standardization is explained and discussed. In addition, multi-language-specific UVM standardization requirements will be presented and language extensions will be proposed to address seamless integration and interoperability between UVM verification frameworks in SystemVerilog and SystemC.
- “An Introduction to the Accellera Functional Safety Working Group Standardization Effort” will be presented by members of the Functional Safety Working Group from 11:30am-12:30pm. Accellera formed a working group of functional safety practitioners and experts from the industry to develop a standard that will provide a standardization definition of the Functional Safety data exchange to improve automation, interoperability, and traceability of the implementation of the Functional Safety guidelines and best practices during the lifecycle. The standard plans to capture a data model, language, or format to exchange data seamlessly among functional safety work products and across layers of the supply chain. This workshop presents some of the challenges in the industry for managing the exchange of data related to functional safety and then the goals and mission of the Accellera Functional Safety Working Group towards a new standard to address those challenges.
Accellera-sponsored UVM Birds of a Feather on Monday, March 1 from 10:30am-11:30am:
The Accellera UVM Working Group has recently delivered a UVM library to match the IEEE 1800.2-2020 specification and is now considering which enhancements and bug fixes to work on next that would most benefit the user community. A complication is that many in the user community are still using older versions of UVM and so would not benefit from improvements to the 1800.2-2020 library. This session will gather feedback from the user community through polling and a live Q&A to understand what could be done to help users get to 1800.2-2020 as well as what types of improvements would be the most useful. Attendance to the Birds of a Feather is free, but registration through DVCon is required to access the platform.
Keynote address on Tuesday, March 2:
This year’s keynote, “Computational Logistics for System and Software Verification,” will be presented by Dr. Paul Cunningham, corporate vice president and general manager of the system verification group at Cadence on Tuesday, March 2 from 1:00pm-2:15pm. In his presentation Dr. Cunningham will introduce the concept of verification throughput and highlight the significant opportunities we have as an industry to dramatically improve verification throughput on modern SoC designs.
Accellera update and presentation of the 2021 Technical Excellence Award:
Following the keynote, Accellera Chair Lu Dai will give a brief update on Accellera activities and Martin Barnasconi, Accellera Technical Committee Chair, will present the 2021 Technical Excellence Award to this year’s recipient. The Accellera Technical Excellence Award recognizes the tremendous achievements of Accellera Working Group members by selecting outstanding contributors to our standards development processes.
In addition to the keynote, the four-day program includes 42 papers, four tutorials, 14 posters, two panels, 18 short workshops, and approximately 20 exhibitors. For the complete DVCon U.S. 2021 schedule, including a list of tutorials, short workshops, panels, posters, exhibitors, and virtual events, visit the program agenda.
For more information and to register, visit the registration page. Registration for the keynote, panels, Birds of a Feather and exhibits-only is free, but registration is required for access.
SystemC Evolution Quarterly Fika Events
Our annual SystemC Evolution Day event is evolving to include more regular events in the form of smaller, regular workshops. Each event is referred to as a Fika to honor the European tradition of sharing a coffee, slowing down a bit, and talking about topics that those in attendance care about.
In addition to the sixth annual SystemC Evolution Day co-located later this year with DVCon Europe 2021, the first SystemC Evolution Fika will take place on March 17, 2021 from 16:00 to 18:00 CET. It will have two presentations: one on SystemC and Python and one focused on the Intel SystemC Compiler.
The SystemC Evolution Fika is free of charge and will be virtual. Anyone interested in the advancement of the SystemC ecosystem is encouraged to attend.
If you have topics you’d like to see included in upcoming Fikas, please let us know by emailing: firstname.lastname@example.org.
For more information, visit the SystemC Evolution Fika page.
DVCon China 2021
DVCon China 2021 will be held at the Renaissance Shanghai Pudong Hotel on May 26, 2021 in Shanghai for local attendees. Stay tuned for more details in the coming weeks.
Interested in becoming a DVCon China 2021 sponsor? Please contact Elyn Han at MCI, DVCon China’s conference management partner, for more information: email@example.com.
Stay Tuned for More Upcoming Accellera Events in 2021
For more information on upcoming events throughout the year, please visit the Accellera Events Page. Information on each event will be updated as soon as it becomes available.
Since its inception, the Accellera-sponsored IEEE Get Program has resulted in more than 119,000 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, including the newly released IEEE 1800.2-2020, visit the Available IEEE Standards page on the Accellera website.
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