Community Newsletter: June 2022
IN THIS ISSUE:
- Message from the Chair
- Standards progress, academic outreach and more
- Accellera at DAC 2022
- Join us for a lunch panel focused on Analog/Mixed-Signal
- Accellera Events Around the Globe
- DVCon Japan – First conference will be virtual June 23
- DVCon India – 7th Annual Conference & Expo to be held in Bangalore in September
- SystemC Evolution Fika – Coming in September! View the videos from the most recent Fika
- DVCon Europe – Save the Date! In-person event will be December 6-7
- SystemC Evolution Day – Co-located with DVCon Europe on December 8
- DVCon China has been postponed to 2023
- Drafts Under Public Review
- UVM SystemC Library 1.0-beta4
- Videos and More
- “Where is the Functional Safety Standard and Why Adopt it” View the video from our Functional Safety Town Hall @ 58th DAC
- SystemC.org – a resource for the SystemC Community
- Videos, Videos and More Videos! View hundreds of presentations on-demand
- IEEE Get Program Update
With summer around the corner, it’s hard to believe we’re almost halfway into 2022. Our working groups have continued to make great progress moving standards development forward.
It seems only yesterday that Accellera introduced the new IP Security Assurance Standard — SA-EDI 1.0. With the standard already robust, the IP Security Assurance Working Group is busy moving it toward IEEE for standardization. IP-XACT is with the IEEE and is close to crossing the finish line to become an IEEE standard. The Portable Stimulus Working Group didn’t take much time to rest after announcing their 2.0 standard; they are already hard at work on a 2.1 update. Our UVM SystemC Library 1.0-beta4 was just released for public review, and we encourage you to download the draft and provide your feedback.
Accellera’s Board of Directors continues to look into ways to expand and strengthen our relationship with the academic community. We added a membership option for Universities a couple of years ago and now have four University members. In 2020 DVCon Europe introduced an Academic Sponsorship option so that students could attend for free, and this year DVCon U.S. offered academic attendees a low student registration rate. Accellera is investigating additional opportunities for engagement, including potential collaboration on university courses, internships, academic recognition of DVCon paper presentations, and more. We are still in the early stages of exploration and look forward to keeping you updated on our progress.
As the U.S. gets back to in-person events, we are looking forward to the Design Automation Conference in July. We invite you to join us for our lunch panel focused on AMS. We anticipate excellent participation and a lively discussion. It is a great start to face-to-face meetings, especially in the summer in San Francisco.
While we are very optimistic about getting together in-person, with COVID on the rise again but society moving closer to a full reopening, we must continue to use caution and stay vigilant.
Lu Dai, Accellera Systems Initiative Chair
Several sessions throughout the Design Automation Conference have presentations that include Accellera standards such as UVM and SystemC. The 59th DAC program is online and can be searched by topic.
Accellera Panel Focused on Analog/Mixed-Signal Standards – Join us for Lunch & Learn from the Experts!
Tuesday, July 12
Moscone West, Room 3024
Topic: “AMS language standards for Design and Verification: Standing still or moving forward?”
We invite you to join us for lunch and a panel discussion focused on the current state of analog/mixed-signal standards, the challenges, and the opportunities. Martin Barnasconi, our Technical Committee Chair, will also provide a brief update on Accellera.
In many application domains such as Communications, Automotive, Biomedical, Aerospace, and Industrial, a solid understanding of analog/RF and mixed-signal concepts is vital to design and verify high quality and robust products. Furthermore, the integration of digital and software technologies in analog- and RF-centric products requires a careful review of the applicability of today’s mixed-signal design, modeling and verification methodologies and flows, and the available tools and languages.
Are today’s AMS language standards sufficient to keep up with the industry needs? What else is required?
The AMS panel will feature industry experts that can shed light on the challenges and opportunities in the mixed-signal design and verification domain and discuss the ongoing standards developments in Accellera on UVM-AMS, SystemC-AMS, and SystemVerilog-AMS as well as available IEEE standards such as SystemVerilog and VHDL-AMS. Panelists will also share their insights into what needs to happen in addition to these initiatives to further advance the mixed-signal design and verification domain.
- Lakshmanan Balasubramanian, Texas Instruments
- Martin Barnasconi, NXP Semiconductors
- Nagu R Dhanwada, IBM
- Peter Grove, Renesas
- Xiang Li, Qualcomm
Moderator: Tom Fitzpatrick, UVM-AMS Working Group Chair
The Accellera-sponsored luncheon is free to DAC attendees, but registration is required.
Accellera Leadership at DAC
“Supply Chain Verification –– Critical Enabler for Next-Generation MedTech Innovations”
Tuesday, July 12
11:35am - 12:25pm
Smart Pavilion, South Hall Moscone
Sponsored by ESD Alliance/Semi
The democratization of chip design is a great catchphrase and captures the effect of the open-source silicon movement that offers the promise of chip design anywhere/anytime. Dig more deeply though, and it is clear some big challenges must be addressed to enable this vision.
A panel of thought leaders and experts will discuss ways in which verification across the supply chain can be improved to support the growing open-source movement, new chip applications, and the impact on manufacturing and packaging. Audience participation will be encouraged.
- Mike Chin, Intel
- Lu Dai, Qualcomm & Accellera Chair
- Dave Kelf, Breker
- Jan Vardaman, TechSearch International
Moderator: Lucio Lanza, Lanza techVentures
Registration with either SEMICON West or the Design Automation Conference is required to attend this session. For more information on the Smart MedTech Sessions visit here.
“Digital Twin Reimagined – One Model to Rule Them All?”
Wednesday, July 13th
This DAC special session will present the opportunities and the challenges of bringing together Digital Twin technologies with semiconductor, electronics HW and SW development techniques. Speakers will cover the characteristics of a Digital Twin, the available modeling, simulation and virtualization platforms, and proposals for how to efficiently integrate the different models and/or frameworks to shape the Digital Twin ecosystem.
Organizer: Martin Barnasconi, NXP Semiconductors and Accellera Technical Committee Chair
- Bryan Ramirez, Siemens EDA
- Manfred Thanner, NXP Semiconductors
- Fred Hannert, General Motors
For more information on this session, visit the DAC program. Registration with the Design Automation Conference is required to attend this presentation.
The first DVCon Japan will be a virtual conference June 23, 2022. The Steering Committee has put together a full day program for attendees with a variety of sessions. Program highlights include a tutorial on Portable Stimulus covering real use cases and a second tutorial “Machine Learning Driven Verification: A Step Function in Productivity and Throughput.” There will also be presentations covering “Formal Verification Sign-Off using the End-to-End Formal Test Bench Methodology,” and “Modeling PSS Action Sequences Using Machine Learning.”
More details on the full program, including the keynote, will be added soon. For the most up-to-date information and to register, please visit the conference website.
Welcome Message from the General Chair
On behalf of the DVCon India 2022 steering committee, it is my pleasure to welcome you all to the 7th edition of the Design and Verification Conference in India planned for September 6-7, 2022. We are bringing DVCon India 2022 as a live, in person conference which makes it the first live event in the VLSI ecosystem in India. The conference will be following the traditional Indian version of a two-day conference with in-depth technical content spreading across both days. We thank you all and the entire ecosystem for the understanding and cooperation throughout this journey.
To read the full welcome letter from Pradeep Salla, DVCon India 2022 General Chair, visit here.
For the latest updates on registration and program information, visit the website.
SystemC Evolution Fika
The next SystemC Evolution Fika workshop will be held September 15. Stay tuned for more information coming soon.
In addition to the annual SystemC Evolution Day, which is co-located with DVCon Europe, SystemC Fikas are smaller online workshops that are free to attend and occur every few months. The workshops are known as Fikas to honor the Fika tradition of sharing a coffee, slowing down a bit, and talking about things that we care about.
The most recent Fika was held in April with a focus on Parallelization of SystemC Simulations. To view the full program and videos visit here. For more information, and to view presentations from other past Fikas, visit here.
Welcome Message from the General Chair
Good News!! DVCon Europe is returning to its usual conference venue in Munich for an in-person conference. It is my pleasure to welcome you all to the 9th edition of DVCon Europe planned on 6th and 7th December 2022, along with Accellera’s co-located SystemC Evolution Day on 8th December 2022.
From COVID 19 to the chip shortage and now the ongoing geopolitical crisis, it seems like we are living in a dramatic part of history, where nothing can be taken for granted. In this ever-changing global scenario, one thing that remains constant is the relevance and importance of science and technology, which heavily depends on our semiconductor industry.
DVCon Europe is the premier European technical conference on system, software, design, verification, validation, and integration. It is a place where the latest methodologies and technologies for the industrial use of tools, languages, and standards for integrated and embedded systems and products are shared and discussed.
To read the full welcome letter from Sumit Jha, DVCon Europe 2022 General Chair, visit here.
SystemC Evolution Day
Co-located with DVCon Europe, SystemC Evolution Day will be held December 8th at the Holiday Inn, Munich, City Centre. The 7th annual workshop is a full-day event focused on the evolution of SystemC standards to advance the SystemC ecosystem. SystemC Evolution Day is intended as a lean, user-centric, hands-on forum bringing together experts from the SystemC user community and the Accellera Working Groups to advance SystemC standards.
More information on the program will be available in the coming months. Videos from the 2021 workshop are available on-demand.
Stay Up to Date with Accellera Events
For more information on upcoming events throughout the year, please visit the Accellera events page. Information will be added as soon as it becomes available.
Due to COVID, DVCon China has been postponed to 2023. Stay tuned for more information coming soon.
A draft of UVM SystemC Library 1.0-beta4 is available for download and public review is open through July 15, 2022. We welcome your feedback and comments as the Working Group prepares for the official release of the UVM SystemC Library 1.0.
If you missed our Town Hall at the 58th Design Automation Conference, “Where is the Functional Safety Standard and Why Adopt It?” you can view the video on-demand. Many market segments have developed systematic processes and techniques to support safety critical design, yet many challenges are still being addressed. Experts from AMD, Arm, Texas Instruments and DARPA discussed many of the issues during the Town Hall moderated by Functional Safety Working Group Chair Alessandra Nardi.
Systemc.org is the new SystemC Community Portal, with online references to just about everything related to SystemC. If you’re looking for the most up-to-date information, as well as what’s relevant to the SystemC Community, systemc.org is the place to start!
Videos, Videos and More Videos!
Looking for information on an Accellera standard or a presentation from one of our events around the globe? Accellera has over 300 videos archived that are accessible to anyone for free.
Since its inception, the Accellera-sponsored IEEE Get Program has resulted in more than 145,879 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEEE Standards page on the Accellera website.
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