Accellera Systems Initiative Launches Working Group to Standardize Interoperability of Multiple Language Verification Environments and Components
Industry invited to join standardization initiative
NAPA, Calif., April 3, 2013- Accellera Systems Initiative (Accellera), an independent non-profit organization focused on the creation and adoption of electronic design automation (EDA) and intellectual property (IP) standards for design and verification, today announces the formation of a new Multi-language Working Group(MLWG). The mission of the MLWG is to create a standard and functional reference for interoperability of multi-language verification environments and components. Accellera is calling for participation in the newly formed group. Accellera members and the industry at large are invited to join the standardization initiative.
The MLWG will consolidate industry requirements and develop a standards-based approach to combine verification environments built in different languages. In addition, a proof-of-concept implementation is proposed to accompany the standard. The MLWG will also look at ways to enable the introduction of UVM (Universal Verification Methodology) concepts in other environments and languages that come from legacy projects. The UVM standard improves interoperability and reduces the cost of repurchasing and rewriting IP for each new project or electronic design automation tool. It also makes it easier to reuse verification components.
"We are excited about the formation of the Multi-language Working Group," said Shishpal Rawat, chair of Accellera Systems Initiative. "This is a natural extension of a universal verification methodology by which legacy verification IP can be used natively. It preserves the industry's investment in verification IP for modules that have already been designed and verified in non-native simulation environments. It alleviates the need for redeveloping verification IP and allows development teams to focus on verification IP for new IP modules."
"SoC designs involve integrating pieces of verification environments that are often implemented with different technologies," said Warren Stapleton, chair of the Multi-language Working Group. "We look forward to the development of a more standardized approach to combining these systems and expanding the influence of the universal verification methodology at the same time."
In addition to its own technical initiatives and working groups, Accellera supports the activities of IEEE standards including IEEE 1076 VHDL, IEEE 1666 SystemC®, IEEE 1685 IP-XACT 2009, IEEE P1735 Encryption and Management of IP, IEEE 1800 SystemVerilog, IEEE 1801 Unified Power Format (UPF) and IEEE 1850 Property Specification Language(PSL).
About Accellera Systems Initiative
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