Tutorial: UVM Tips and Tricks Plus Preparing for IEEE UVM

UVM - Universal Verification Methodology

Presented at DVCon U.S. 2016 on February 29, 2016

Debugging UVM testbenches can be extremely difficult because errors often appear in lines of SystemVerilog code that make up the UVM package, as opposed to the user written code. There are also a number of common errors, that are hard to recognize because the compiler gets off on the wrong track early and never recovers. Most of these errors can easily be eliminated by following a structured approach to debugging that targets these common errors first. This tutorial delivers a plethora of tips and tricks to alleviate the struggle. It walks you through an introduction of UVM testbench features, includes real-world examples including common errors and fixes, and details how to use the built in debugging features in UVM.

This tutorial also includes changes to the UVM standard as it makes the great leap to the IEEE.

The tutorial is split into three sections:

  • Part 1: Part 1: UVM Compile Time Tips and Tricks
    Doug Perry, Doulos

  • Part 2: UVM Runtime Tips and Tricks
    Srivatsa Vasudevan, Synopsys; Slides by Srinivasan Venkataramanan, VerifWorks 

  • Part 3: Accellera Standards Update - UVM and IEEE-1800.2
    Srivatsa Vasudevan, Synopsys
    PDF only (Video not available)

View slides >



Thanks to our Sponsors

CadenceMentor, a Siemens BusinessSynopsys